View MAX17499BAUB_3141165.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max17499/max17500 current-mode pwm con- trollers contain all the control circuitry required for the design of wide-input-voltage isolated and nonisolated power supplies. the max17499 is well suited for low input voltage (9.5v dc to 24v dc) power supplies. the max17500 is well suited for universal input (rectified 85v ac to 265v ac) or telecom (-36v dc to -72v dc) power supplies. the ics contain an internal error amplifier that regulates the tertiary winding output voltage that is used in prima- ry-side-regulated isolated power supplies. primary-side regulation eliminates the need for an optocoupler. an input undervoltage lockout (uvlo) is provided for pro- gramming the input-supply start voltage and to ensure proper operation during brownout conditions. an open- drain uvlo flag output, with 210s internal delay, allows the sequencing of a secondary-side controller. the input-supply start voltage is externally programma- ble with a voltage-divider. a uvlo/en input is used to shut down the devices. internal digital soft-start elimi- nates output voltage overshoot. the max17500 has an internal bootstrap uvlo with large hysteresis that requires a minimum 23.6v for start- up. the max17499 does not have the internal bootstrap uvlo and can be biased directly from a minimum volt- age of 9.5v. the switching frequency for the ics is programmable with an external resistor. the max17499a/max17500a provide a 50% maximum duty-cycle limit, while the max17499b/max17500b provide a 75% maximum duty-cycle limit. these devices are available in 10-pin max ? packages and are rated for operation over the -40c to +125c temperature range. features current-mode control programmable switching frequency up to 625khz accurate uvlo threshold (1%) open-drain uvlo flag output with internal delay 36v to 72v telecom voltage range universal offline input voltage range rectified 85v ac to 265v ac (max17500) 9.5v to 24v input (max17499) digital soft-start internal bootstrap uvlo with large hysteresis (max17500) internal error amplifier with 1.5% accurate reference 50 a (typ) startup supply current 50% maximum duty-cycle limit (max17499a/max17500a) 75% maximum duty-cycle limit (max17499b/max17500b) 60ns cycle-by-cycle current-limit propagation delay available in tiny 10-pin max packages applications 1/2, 1/4, and 1/8 brick power modules high-efficiency, isolated telecom power supplies networking/servers isolated keep-alive power supplies 12v boost and sepic regulators isolated and nonisolated high-brightness led power supplies industrial power conversion max17499/max17500 current-mode pwm controllers with programmable switching frequency ________________________________________________________________ maxim integrated products 1 ordering information 19-5485; rev 1; 7/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. warning: the ics are designed to work with high voltages. exercise caution. + denotes a lead(pb)-free/rohs-compliant package. evaluation kit available selector guide appears at end of data sheet. part d max (%) startup voltage (v) temp range pin-package max 17499 aaub+ 50 9.5 -40c to +125c 10 max MAX17499BAUB+ 75 9.5 -40c to +125c 10 max max 17500 aaub+ 50 22 -40c to +125c 10 max max17500baub+ 75 22 -40c to +125c 10 max max is a registered trademark of maxim integrated products, inc.
max17499/max17500 current-mode pwm controllers with programmable switching frequency 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = +12v (for max17500, bring v in up to 23.6v for startup), 10nf bypass capacitors at in and v cc , r12 = 15k (max17499a/ max17500a), r12 = 7.5k (max17499b/max17500b), r15 = 1k , c6 = 100nf (see the typical application circuit ), ndrv = open, v uvlo/en = +1.4v, v fb = +1.0v, comp = open, v cs = 0v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to gnd ...............................................................-0.3v to +30v in clamp (internal shunt) current .........................................5ma v cc to gnd ............................................................-0.3v to +13v fb, comp, uvlo/en, rt, cs to gnd .....................-0.3v to +6v uflg to gnd .........................................................-0.3v to +30v ndrv to gnd.............................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70c) 10-pin max (derate 5.6mw/c above +70c) ........444.4mw operating temperature range .........................-40c to +125c storage temperature range ............................-65c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units uvlo/startup bootstrap uvlo wake-up level v suvr v in rising (max17500 only) 19.68 21.6 23.60 v bootstrap uvlo shutdown level v suvf v in falling (max17500 only) 9.05 9.74 10.43 v uvlo/en wake-up threshold v ulr2 uvlo/en rising 1.215 1.23 1.245 v uvlo/en shutdown threshold v ulf2 uvlo/en falling 1.14 1.17 1.20 v uvlo/en input current i uvlo v uvlo/en 2v -50 +50 na uvlo/en hysteresis 60 mv in supply current in uvlo i start v in = 19v, max17500 only when in bootstrap uvlo 50 90 a in input voltage range v in max17499 only 9.5 24.0 v uvlo/en steps up from 1v to 1.4v 3 uvlo/en to uflg propagation delay (figure 3) uvlo/en steps down from 1.4v to 1v 0.6 s t extr uvlo/en steps up from 1v to 1.4v 3 10 ms uvlo/en to ndrv propagation delay (figure 3) t extf uvlo/en steps down from 1.4v to 1v 150 210 300 s t buvr v in steps up from 9v to 24v (max17500 only) 5 bootstrap uvlo propagation delay t buvf v in steps down from 24v to 9v (max17500 only) 1 s uflg low output voltage v uflg i uflg = 5ma sinking 1.5 v uflg high output leakage current v uflg = 25v 0.1 1 a internal supply v cc regulator set point v ccsp v in = 10.8v to 24v, sinking 1a to 20ma from v cc 7.0 10.5 v in supply current after startup i in v in = 24v 2 4 ma shutdown supply current uvlo/en = low 50 90 a
max17499/max17500 current-mode pwm controllers with programmable switching frequency _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = +12v (for max17500, bring v in up to 23.6v for startup), 10nf bypass capacitors at in and v cc , r12 = 15k (max17499a/ max17500a), r12 = 7.5k (max17499b/max17500b), r15 = 1k , c6 = 100nf (see the typical application circuit ), ndrv = open, v uvlo/en = +1.4v, v fb = +1.0v, comp = open, v cs = 0v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units gate driver r on ( low ) measured at ndrv sinking 100ma 2 4 driver output impedance r on ( high ) measured at ndrv sourcing 20ma 4 10 driver peak sink current 1a driver peak source current 0.65 a pwm comparator comparator offset voltage v pwm v comp - v cs 1.24 1.38 1.54 v cs input bias current i cs v cs = 0v -4 +4 a comparator propagation delay t pwm change in v cs = 0.1v 60 ns current-limit comparator current-limit trip threshold v cs 900 1000 1100 mv cs input bias current i cs v cs = 0v -4 +4 a propagation delay from comparator input to ndrv t pdcs 100mv overdrive 60 ns in clamp voltage in clamp voltage v inc 2ma sink current (note 2) 24.1 26.1 29.0 v error amplifier voltage gain r load = 100k 80 db unity-gain bandwidth r load = 100k , c load = 200pf 2 mhz phase margin r load = 100k , c load = 200pf 65 d eg r ees fb input offset voltage 1 mv comp high voltage i comp = 0a 2.5 v comp low voltage i comp = 0a 1.1 v source current 0.5 ma sink current 0.5 ma reference voltage v ref (note 3) 1.230 v reference voltage accuracy -1.5 +1.5 % fb input bias current -50 +50 na comp short-circuit current 8ma digital soft-start 1984 ndrv cycles soft-start duration t ss f sw = 350khz 5.6 ms reference voltage steps during soft-start 31 steps reference voltage step 39.67 mv
max17499/max17500 current-mode pwm controllers with programmable switching frequency 4 _______________________________________________________________________________________ note 1: all devices are 100% tested at t a = +125?. all limits over temperature are guaranteed by characterization. note 2: the max17500 is intended for use in universal input power supplies. the internal clamp circuit at in is used to prevent the bootstrap capacitor (c1 in figure 1) from charging to a voltage beyond the absolute maximum rating of the device when uvlo/en is low (shutdown mode). externally limit the maximum current to in (hence to clamp) to 2ma maximum when uvlo/en is low. clamp currents higher than 2ma may result in a clamp voltage higher than 30v, thus exceeding the absolute maximum rating for in. for the max17499, do not exceed the 24v maximum operating voltage of the device. note 3: v ref is measured with fb connected to comp (see the functional diagram ). note 4: the oscillator in the max17499a/max17500a is capable of operating up to 2500khz. however, the ndrv switching fre- quency is limited to operate up to 625khz. thus, the oscillator frequency for the max17499a/max17500a must be limited to 1250khz (maximum). electrical characteristics (continued) (v in = +12v (for max17500, bring v in up to 23.6v for startup), 10nf bypass capacitors at in and v cc , r12 = 15k ? (max17499a/ max17500a), r12 = 7.5k ? (max17499b/max17500b), r15 = 1k ? , c6 = 100nf (see the typical application circuit ), ndrv = open, v uvlo/en = +1.4v, v fb = +1.0v, comp = open, v cs = 0v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 1) bootstrap uvlo wake-up level vs. temperature max17499/500 toc01 temperature ( c) v in (v) 60 35 10 -15 21.4 21.5 21.6 21.7 21.8 21.3 -40 85 max17500 v in rising bootstrap uvlo shutdown level vs. temperature max17499/500 toc02 temperature ( c) v in (v) 60 35 10 -15 9.5 9.7 9.9 10.1 10.3 9.3 -40 85 max17500 v in falling uvlo/en wake-up threshold vs. temperature max17499/500 toc03 temperature ( c) v uvlo/en (v) 60 35 10 -15 1.226 1.228 1.230 1.232 1.234 1.236 1.224 -40 85 uvlo/en rising typical operating characteristics (v uvlo/en = +1.4v, v fb = +1v, comp = open, v cs = 0v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units oscillator oscillator frequency range f osc 50 2500 khz f osc = 200khz to 800khz -10 +10 oscillator frequency accuracy f osc = 50khz to 2500khz -20 +20 % max17499a/max17500a, f sw = f osc /2 25 625 ndrv switching frequency (note 4) f sw max17499b/max17500b, f sw = f osc /4 12.5 625.0 khz max17499a/max17500a 50 maximum duty cycle d max max17499b/max17500b 75 %
max17499/max17500 current-mode pwm controllers with programmable switching frequency _______________________________________________________________________________________ 5 uvlo/en shutdown threshold vs. temperature max17499/500 toc04 temperature ( c) v uvlo/en (v) 60 35 10 -15 1.155 1.160 1.165 1.170 1.175 1.180 1.150 -40 85 uvlo/en falling v in supply current in uvlo vs. temperature max17499/500 toc05 temperature ( c) i start ( a) 60 35 10 -15 50 55 60 65 45 -40 85 v in = 19v max17500 when in bootstrap uvlo v in supply current after startup vs. temperature max17499/500 toc06 temperature ( c) i in (ma) 60 35 10 -15 1.6 1.7 1.8 1.9 2.0 1.5 -40 85 v in = 24v f sw = 350khz v cc regulator set point vs. temperature max17499/500 toc07 temperature ( c) v cc (v) 60 35 10 -15 9.2 9.4 9.6 9.8 9.0 -40 85 v in = 19v ndrv not switching ndrv switching f sw = 350khz v cc regulator set point vs. temperature max17499/500 toc08 temperature ( c) v cc (v) 60 40 -20 0 20 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.1 -40 80 10ma load v in = 19v 20ma load current-limit trip threshold vs. temperature max17499/500 toc09 temperature ( c) current-limit trip threshold (v) 60 35 10 -15 0.97 0.98 0.99 1.00 1.01 1.02 0.96 -40 85 -3 mean +3 total number of devices = 140 current-limit trip threshold max17499/500 toc10 current-limit trip threshold (v) percentage of units (%) 1.022 0.993 1.007 0.978 10 20 30 40 50 60 0 0.964 1.036 total number of devices = 140 switching frequency vs. temperature max17499/500 toc11 temperature ( c) switching frequency (khz) 60 35 10 -15 330 335 340 345 350 355 325 -40 85 -3 mean +3 total number of devices = 140 switching frequency max17499/500 toc12 switching frequency (khz) percentage of units (%) 354.0 340.3 347.2 333.5 10 20 30 40 50 60 0 326.7 360.8 total number of devices = 140 typical operating characteristics (continued) (v uvlo/en = +1.4v, v fb = +1v, comp = open, v cs = 0v, t a = +25?, unless otherwise noted.)
max17499/max17500 current-mode pwm controllers with programmable switching frequency 6 _______________________________________________________________________________________ switching frequency vs. timing resistor max17499/500 toc13 timing resistor (k ) switching frequency (khz) 100 10 100 1000 1 1000 10 max17499a/max17500a propagation delay from current-limit comparator input to ndrv vs. temperature max17499/500 toc14 temperature ( c) t pdcs (ns) 60 35 10 -15 45 50 55 60 40 -40 85 uvlo/en-to-ndrv propagation delay vs. temperature max17499/500 toc15 temperature ( c) uvlo delay (ms) 60 35 10 -15 1 2 3 4 5 6 0 -40 85 uvlo/en rising uvlo/en falling 206 s uvlo/en-to-uflg propagation delay vs. temperature max17499/500 toc16 temperature ( c) uvlo delay ( s) 60 35 10 -15 1 2 3 4 5 6 0 -40 85 uvlo/en rising uvlo/en falling reference voltage vs. temperature max17499/500 toc17 temperature ( c) reference voltage (v) 60 35 10 -15 1.229 1.230 1.231 1.232 1.228 -40 85 v in = 12v input current vs. in voltage max17499/500 toc18 in voltage (v) input current (ma) 18 17 16 15 14 13 12 11 1.64 1.68 1.72 1.76 1.80 1.60 10 19 uvlo/en = 1.4v ndrv switching at 350khz input clamp voltage vs. temperature max17499/500 toc19 temperature ( c) input clamp voltage (v) 60 40 20 0 -20 25.2 25.4 25.6 25.8 26.0 26.2 26.4 26.6 26.8 27.0 25.0 -40 80 i in = 2ma ndrv low-output impedance vs. temperature max17499/500 toc20 temperature ( c) r on ( ) 60 35 10 -15 1.4 1.6 1.8 2.0 2.2 2.4 1.2 -40 85 v in = 24v sinking 100ma typical operating characteristics (continued) (v uvlo/en = +1.4v, v fb = +1v, comp = open, v cs = 0v, t a = +25c, unless otherwise noted.)
max17499/max17500 current-mode pwm controllers with programmable switching frequency _______________________________________________________________________________________ 7 pin description pin name function 1 uvlo/en externally programmable undervoltage lockout. uvlo/en programs the input start voltage. connect uvlo/en to gnd to disable the device. ndrv stops switching approximately 210s after the uvlo/en voltage falls below 1.17v. 2 uflg open-drain undervoltage flag output. uflg is asserted low as soon as the uvlo/en voltage falls below its threshold. 3 fb error-amplifier inverting input 4 comp error-amplifier output 5cs current-sense input. current-sense connection for pwm regulation and cycle-by-cycle current limit. connect to the high side of the sense resistor. an rc filter may be necessary to eliminate leading-edge spikes. current-limit trip voltage is 1v. 6rt oscillator timing resistor input. an rc network may be required to reduce jitter (see the typical application circuit ). ndrv high-output impedance vs. temperature max17499/500 toc21 temperature ( c) r on ( ) 60 35 10 -15 3.4 3.8 4.2 4.6 5.0 3.0 -40 85 sourcing 20ma error amplifier open-loop gain and phase vs. frequency frequency (hz) gain (db) phase (degrees) 100 -60 80 60 40 20 0 -20 -40 120 -200 80 40 0 -40 -80 -120 -160 1 0.1 10 100 1k 10k 100k 1m 10m 100m max17499/500 toc22 gain phase typical operating characteristics (continued) (v uvlo/en = +1.4v, v fb = +1v, comp = open, v cs = 0v, t a = +25c, unless otherwise noted.) 1 2 3 4 5 10 9 8 7 6 in + v cc ndrv gnd comp fb uflg uvlo/en max17499 max17500 max top view rt cs pin configuration
max17499/max17500 detailed description the max17499/max17500 current-mode pwm con- trollers are ideal for isolated and nonisolated power- supply applications. the devices offer an accurate input startup voltage programmable through the uvlo/en input. this feature prevents the power supply from entering a brownout condition in case the input voltage sags below its minimum value. this is important since switching power supplies increases their input supply current as the input voltage drops to keep the output power constant. in addition to this externally adjustable uvlo feature, the max17500 also offers a bootstrap uvlo with a large hysteresis (11.9v) and very low startup and operating current, which result in an efficient universal input power supply. the switching frequency of the devices is programmable with an external resistor. the max17500 is well suited for universal input (recti- fied 85v ac to 265v ac) or telecom (-36v dc to -72v dc) power supplies. the max17499 is well suited for low-input-voltage (9.5v dc to 24v dc) power sup- plies. the devices include an internal clamp at in to prevent the input voltage from exceeding the absolute maximum rating (see note 2 at the end of the electrical characteristics table). the input is clamped when the devices are started with a bleed resistor (r1 in figure 1) from a high input voltage and the uvlo/en input is low. the clamp can safely sink up to 2ma current. current-mode pwm controllers with programmable switching frequency 8 _______________________________________________________________________________________ 8 9 10 3 2 1 uvlo/en in 7 4 v cc ndrv gnd uflg fb comp 6 5 rt cs t1 r3 r2 r12 r1 r4 c5 c2 c2 c1 c4 d2 d1 c6 r11 v supply 0v r13 r14 v out r15 q1 max17500 figure 1. nonisolated power supply with programmable input-supply start voltage pin description (continued) pin name function 7 gnd ground connection 8 ndrv external n-channel mosfet gate connection 9v cc gate-drive supply. internally generated supply from in. decouple v cc with a 10nf or larger capacitor to gnd. 10 in in supply. decouple with a 10nf or larger capacitor to gnd. for bootstrapped operation (max17500), connect a startup resistor from the input supply line to in. connect the bias winding supply to in also (see the typical application circuit ). for the max17499, connect in directly to the 9.5v to 24v supply.
power supplies designed with the max17500 use a high-value startup resistor, r1, that charges a reservoir capacitor, c1 (see figure 1). during this initial period, while the voltage is less than the internal bootstrap uvlo threshold, the device typically consumes only 50a of quiescent current. this low startup current and the large bootstrap uvlo hysteresis help to minimize the power dissipation across r1 even at the high end of the universal ac input voltage (265v ac). the devices include a cycle-by-cycle current limit that turns off the gate drive to the external mosfet when- ever the internally set threshold of 1v is exceeded. when using the max17500 in bootstrapped mode, if the power-supply output is shorted, the tertiary winding voltage drops below the internally set threshold caus- ing the uvlo to turn off the gate drive to the external power mosfet. this reinitiates a startup sequence with soft-start. current-mode control loop the advantages of current-mode control over voltage- mode control are twofold. first, there is the feed-for- ward characteristic brought on by the controllers ability to adjust for variations in the input voltage on a cycle-by-cycle basis. secondly, the stability require- ments of the current-mode controller are reduced to that of a single-pole system unlike the double pole in voltage-mode control. the devices use a current-mode control loop where the output of the error amplifier (comp) is compared to the current-sense voltage at cs. when the current-sense signal is lower than the noninverting input of the cpwm comparator, the output of the cpwm comparator is low and the switch is turned on at each clock pulse. when the current-sense signal is higher than the inverting input of the cpwm, the output of the cpwm comparator goes high and the switch is turned off. undervoltage lockout the devices provide a uvlo/en input. the threshold for uvlo is 1.23v with 60mv hysteresis. before any operation can commence, the voltage on uvlo/en has to exceed 1.23v. the uvlo circuit keeps the cpwm comparator, ilim comparator, oscillator, and output dri- ver shut down to reduce current consumption (see the functional diagram ). use this uvlo/en input to program the input-supply start voltage. for example, a reasonable start voltage for a 36v to 72v telecom range is usually 34v. calculate the resistor-divider values, r2 and r3 (see figure 1) by using the following formulas: where i uvlo is the uvlo/en input current (50na max), and v ulr2 is the uvlo/en wake-up threshold (1.23v). v in is the value of the input-supply voltage where the power supply must start. the value of r3 is calculated to minimize the voltage-drop error across r2 as a result of the input bias current of the uvlo/en input. max17500 bootstrap uvlo in addition to the externally programmable uvlo func- tion offered in both devices, the max17500 includes an internal bootstrap uvlo that is very useful when designing high-voltage power supplies (see the functional diagram ). this allows the device to bootstrap itself during initial power-up. the max17500 attempts to start when v in exceeds the bootstrap uvlo threshold of 21.6v. during startup, the uvlo circuit keeps the cpwm comparator, ilim comparator, oscillator, and output driver shut down to reduce current consumption. once v in reaches 21.6v, the uvlo circuit turns on the cpwm and ilim comparators, the oscillator, and allows the output driver to switch. if v in drops below 1.17v, the uvlo circuit shuts down the cpwm comparator, ilim comparator, oscillator, and output driver returning the max17500 to the low-current startup mode. startup operation the max17499 starts up when the voltage at in exceeds 9.5v and the uvlo/en input is greater than 1.23v. however, the max17500 requires that, in addi- tion to meeting the specified startup conditions for the max17499, the voltage at in exceeds the bootstrap uvlo threshold of 21.6v. r vv ivv r vv v ulr in uvlo in ulr in ulr 3 500 2 2 2 2 ? ? = ? () u ulr r 2 3 max17499/max17500 current-mode pwm controllers with programmable switching frequency _______________________________________________________________________________________ 9
max17499/max17500 for the max17500, the voltage at in is normally derived from a tertiary winding of the transformer. however, at startup there is no energy being delivered through the transformer; hence, a special bootstrap sequence is required. figure 2 shows the voltages at v in and v cc during startup. initially, both v in and v cc are 0v. after the line voltage is applied, c1 charges through the startup resistor, r1, to an intermediate voltage. at this point, the internal regulator begins charging c2 (see figure 1). only 50a of the current supplied through r1 is used by the max17500; the remaining input current charges c1 and c2. the charging of c2 stops when the v cc voltage reaches approximately 9.5v, while the voltage across c1 continues rising until it reaches the wake-up level of 21.6v. once v in exceeds the boot- strap uvlo threshold, ndrv begins switching the mosfet and transfers energy to the secondary and tertiary outputs. if the voltage on the tertiary output builds to higher than 9.74v (the bootstrap uvlo lower threshold), then startup has been accomplished and sustained operation commences. if v in drops below 9.74v before startup is complete, the device goes back to low-current uvlo. in this case, increase the value of c1 to store enough energy to allow for the voltage at the tertiary winding to build up. uvlo flag (uflg) the devices have an open-drain undervoltage flag out- put (uflg). when used with an optocoupler, the uflg output can serve to sequence a secondary-side con- troller. an internal 210s delay occurs the instant the voltage on uvlo/en drops below 1.17v until ndrv stops switching. this allows for the uflg output to change state before the devices shut down (figure 3). when the voltage at the uvlo/en is above the thresh- old, uflg is high impedance. when uvlo/en is below the threshold, uflg goes low. uflg is not affected by bootstrap uvlo (max17500). current-mode pwm controllers with programmable switching frequency 10 ______________________________________________________________________________________ max17499/max17500 fig02 100ms/div v cc 2v/div v in 5v/div 0v figure 2. v in and v cc during startup when using the max17500 in bootstrapped mode (figure 1) v uvlo/en low low high- v uflg v ndrv shutdown shutdown t extr 3ms 1.23v ( 1%) 1.17v (typ) t extf 210 s 0.6 s 3 s ndrv switching figure 3. uvlo/en and uflg operation timing
soft-start the devices soft-start feature allows the output voltage to ramp up in a controlled manner, eliminating voltage overshoot. the devices reference generator that is internally connected to the error amplifier soft-starts to achieve superior control of the output voltage under heavy- and light-load conditions. soft-start begins after uvlo is deasserted (v in is above 21.6v for the max17500, v in is above 9.5v for the max17499, and the voltage on uvlo/en is above 1.23v). the voltage applied to the noninverting node of the amplifier ramps from 0 to 1.23v in 1984 ndrv switching cycles. use the following formula to calculate the soft-start time (t ss ): where f ndrv is the switching frequency at the ndrv output. figure 4 shows the soft-start regulated output of a power supply using the max17500 during startup. n-channel mosfet switch driver the ndrv output drives an external n-channel mosfet. the internal regulator output (v cc ), set to approximately 9v, drives ndrv. for the universal input voltage range, the mosfet used must withstand the dc level of the high-line input voltage plus the reflected voltage at the primary of the transformer. most applications that use the discontinuous flyback topology require a mosfet rated at 600v. ndrv can source/sink in excess of 650ma/ 1000ma peak current; therefore, select a mosfet that ma yields acceptable conduction and switching losses. oscillator/switching frequency use an external resistor at rt to program the devices internal oscillator frequency between 50khz and 2.5mhz. the max17499a/max17500a output switching frequen- cy is one-half the programmed oscillator frequency with a 50% duty cycle. the max17499b/max17500b output switching frequency is one-quarter of the programmed oscillator frequency with a 75% duty cycle. the max17499a/max17500a and max17499b/ max17500b have programmable output switching fre- quencies from 25khz to 625khz and 12.5khz to 625khz, respectively. use the following formulas to determine the appropriate value of resistor r12 (see figure 1) needed to generate the desired output switching frequency (f sw ) at the ndrv output: where r12 is the resistor connected from rt to gnd (see figure 1). connect an rc network in parallel with r12 as shown in figure 1. the rc network should consist of a 100nf capacitor, c6, (for stability) in series with resistor r15, which serves to further minimize jitter. use the following formula to determine the value of r15: for example, if r12 is 4k , r15 becomes 707 . internal error amplifier the devices include an internal error amplifier to regu- late the output voltage in the case of a nonisolated power supply (see figure 1). for the circuit in figure 1, calculate the output voltage using the following equation: where v ref = 1.23v. the amplifiers noninverting input is internally connected to a digital soft-start circuit that gradually increases the reference voltage during start- up applied to this input. this forces the output voltage to come up in an orderly and well-defined manner under all load conditions. the error amplifier may also be used to regulate the ter- tiary winding output, which implements a primary-side- regulated, isolated power supply (see figure 6). for the v r r v out ref =+ ? ? ? ? ? ? 1 13 14 rr 15 88 9 12 1 4 . = () r f for the max a max a r sw 12 10 2 17499 17500 12 10 = . = = 10 4 17499 17500 10 f for the max b max b sw . t f ss ndrv = 1984 max17499/max17500 current-mode pwm controllers with programmable switching frequency ______________________________________________________________________________________ 11 max17499/max17500 fig04 2ms/div v out 2v/div 100ma load on/v out1 100ma load on/v out2 figure 4. primary-side output voltage soft-start during initial startup for the circuit in figure 6
max17499/max17500 circuit in figure 6, calculate the output voltage using the following equation: where n s is the number of secondary winding turns, n t is the number of tertiary winding turns, and both v d6 and v d2 are the diode drops at the respective outputs. current limit the current-sense resistor (r4 in figure 1), connected between the source of the mosfet and ground, sets the current limit. the current-limit comparator has a voltage trip level (v cs ) of 1v. use the following equation to cal- culate the value of r4: where i pri is the peak current in the primary side of the transformer, which also flows through the mosfet. when the voltage produced by this current (through the current-sense resistor) exceeds the current-limit com- parator threshold, the mosfet driver (ndrv) termi- nates the current on-cycle within 60ns (typ). use a small rc network to filter out the leading-edge spikes on the sensed waveform when needed. set the corner frequency between 2mhz and 10mhz. applications information startup time considerations for power supplies using the max17500 the bypass capacitor at in, c1, supplies current imme- diately after the max17500 wakes up (see figure 1). the size of c1 and the connection configuration of the tertiary winding determine the number of cycles avail- able for startup. large values of c1 increase the start- up time but also supply gate charge for more cycles during initial startup. if the value of c1 is too small, v in drops below 9.74v because ndrv does not have enough time to switch and build up sufficient voltage across the tertiary output, which powers the device. the device goes back into uvlo and does not start. use a low-leakage capacitor for c1 and c2. typically, offline power supplies keep startup times to less than 500ms even in low-line conditions (85v ac input for universal offline or 36v dc for telecom appli- cations). size the startup resistor, r1, to supply both the maximum startup bias of the device (90a) and the charging current for c1 and c2. the bypass capacitor, c2, must charge to 9.5v and c1 to 24v, all within the desired time period of 500ms. because of the internal soft-start time of the max17500 (approximately 5.6ms when f sw = 350khz), c1 must store enough charge to deliver current to the device for at least this much time. to calculate the approximate amount of capacitance required, use the following formula: where i in is the max17500s internal supply current (2ma) after startup, q gtot is the total gate charge for q1, f sw is the max17500s switching frequency (350khz), v hyst is the bootstrap uvlo hysteresis (approximately 12v), and t ss is the internal soft-start time (5.6ms). example: i g = (8nc) (350khz) ? 2.8ma choose a 2.2f standard value (assuming 350khz switching frequency). assuming c1 > c2, calculate the value of r1 as follows: where v in(min) is the minimum input supply voltage for the application (36v for telecom), v suvr is the boot- strap uvlo wake-up level (23.6v max), and i start is the in supply current at startup (90a max). for example: choose a 61.9k standard value. ()(.) () . ()( i vf ms ma r v c1 24 2 2 500 0 105 1 36 2 == ? ? 4 4 0 105 90 61 5 v ma a k ) (. ) ( ) . + = i vc ms r vv ii c suvr in min suvr cs 1 1 1 500 1 = ? ? + () () t tart c ma ma ms v f 1 22856 12 224 = + = (.)(.) . iq f c iit v ggtotsw in g ss hyst = = + 1 ()() r v i cs pri 4 = v n n r r vvv out s t ref d d =+ ? ? ? ? ? ? + ? ? ? ? ? ? ? 1 1 2 62 current-mode pwm controllers with programmable switching frequency 12 ______________________________________________________________________________________
choose a higher value for r1 than the one calculated in the previous equation if a longer startup time can be tolerated to minimize power loss on this resistor. the above startup method is applicable to a circuit simi- lar to the one shown in figure 1. in this circuit, the ter- tiary winding has the same phase as the output windings. thus, the voltage on the tertiary winding at any given time is proportional to the output voltage and goes through the same soft-start period as the output voltage. the minimum discharge time of c1 from 21.6v to 9.74v must be greater than the soft-start time of 5.6ms. another method for bootstrapping the power supply is to use a bias winding that is in-phase with the mosfet on-time (see figure 5). in this case, the amount of capacitance required at in (c1) is much smaller. however, the input voltage cannot have a range greater than approximately 2:1 (primary-winding volt- age to bias-winding voltage ratio). for hiccup-mode fault protection, make the bias wind- ing in-phase with the output, then the power-supply hic- cups and soft-starts under output short-circuit conditions. the power supply does not hiccup if the bias winding is in-phase with the mosfet on-time. max17499/max17500 current-mode pwm controllers with programmable switching frequency ______________________________________________________________________________________ 13 v cc comp fb gnd cs ndrv uvlo/en v in r1 r2 r3 r4 d1 t1 c1 c2 r5 r6 r7 u2 opto trans rt uflg c6 r15 r12 c4 in max17500a u1 c3 u3 tl431 u2 opto led r9 v out r8 r10 d2 q1 figure 5. secondary-side regulated, isolated power supply
max17499/max17500 primary-side-regulated, isolated telecom power supply figure 6 shows a complete circuit of a dual-output power supply with a 36v to 72v telecom voltage range. an important aspect of this power supply is that it is pri- mary-side regulated. the regulation through the tertiary winding also supplies bias for the max17500. in the circuit of figure 6, cross-regulation has been improved (tertiary and 5v outputs) by using chip induc- tors, l1 and l2, and r7 || r12 across c12. r7 || r12 presents enough loading on the tertiary winding output to allow 10% load regulation on the 5v output over a 150ma to 1.5a load current range (figure 7). current-mode pwm controllers with programmable switching frequency 14 ______________________________________________________________________________________ max17500a u1 +vin uflg -vin vout2 15v/100ma 5v/1.5a sgnd vout1 sgnd 1 2 1 2 3 3 2 1 4 4 6 7 8 5 t1 d2 d3 open d6 d8 d1 10 d7 open r12 1.2k 7 9 8 6 c6 0.0047 f 250v ac c3 68 f 6.3v 5t 12t d5 c15 1 f d4 l1 c13 1 f c4 22 f 6.3v 28t 35 h 15t 5 n1 irf7464 r7 1.2k r8 open c10 open r5 0.600 1% r15 750 c16 1 f 35v r6 33k c5 47 f 25v l2 fb_p in 36v to 72v in +vin 10 in ndrv cs gnd fb_p rt 8 5 6 7 fb comp uvlo/en uflg note: mosfet n1 = ir irf7464. v cc ju1 3 4 1 2 9 +vin c12 15 f 35v r14 14.3k 1% c17 open c9 100pf c14 3900pf r4 51.1k r3 1.37m 1% r9 75k 1% r2 2.49k 1% r1 22.6k 1% r13 10k c8 open c7 0.22 f c11 0.22 f c19 open c18 0.1 f r11 100 uflg_pull shdn r10 4.7 c2 1 f 100v c1 1 f 100v figure 6. primary-side-regulated, dual-output, isolated telecom power supply 5v output load regulation max17499/max17500 fig07 i out (a) v out (v) 1.35 1.20 0.30 0.45 0.60 0.90 0.75 1.05 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 4.8 0.15 1.50 no load at 15v output v in+ = 40v v in- = 0v figure 7. output voltage regulation for the circuit in figure 6
figure 8 shows the 12v to 15v output boost regulator. layout recommendations typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high dv/dt surfaces. for example, traces that carry the drain current often form high di/dt loops. similarly, the heatsink of the mosfet presents a dv/dt source; there- fore, minimize the surface area of the heatsink as much as possible. keep all pcb traces carrying switching currents as short as possible to minimize current loops. use a ground plane for best results. the pins of the max package are positioned to allow easy interfacing to the external mosfet. for universal ac input design, follow all applicable safety regulations. offline power supplies may require ul, vde, and other similar agency approvals. to avoid noise coupling of signals from rt to ndrv, route traces from rt away from ndrv. max17499/max17500 current-mode pwm controllers with programmable switching frequency ______________________________________________________________________________________ 15 v cc comp fb gnd cs ndrv uvlo/en 0v 12v r2 r3 r1 c1 rt uflg c6 r15 r12 c4 in max17499 c2 c3 r5 r6 15v d1 q1 l1 figure 8. 12v to 15v output boost regulator
max17499/max17500 current-mode pwm controllers with programmable switching frequency 16 ______________________________________________________________________________________ 8 9 10 3 2 1 uvlo/en in 7 4 v cc ndrv gnd uflg fb comp 6 5 rt cs t1 r3 r2 r5 r12 r1 r4 c5 36v to 72v + - c2 c2 c1 c4 d2 d1 c6 r11 v out r15 r6 q1 max17500 typical application circuit
max17499/max17500 current-mode pwm controllers with programmable switching frequency ______________________________________________________________________________________ 17 selector guide * the max17499 does not have an internal bootstrap uvlo. the max17499 starts operation as long as v in is higher than 9.5v and uvlo/en is higher than 1.23v. part* bootstrap uvlo startup voltage (v) max duty cycle (%) max17499a no 9.5 50 max17499b no 9.5 75 max17500a yes 22 50 max17500b yes 22 75 chip information process: bicmos driver fb cs ndrv gnd in comp uvlo/en in clamp 26.1v *max17500 only * uflg v cc max17499 max17500 error amp cpwm uvlo rt oscillator ilim s r reg_ok regulator (internal 5.25v supply) in v l v cc q 1.23v 1.17v v cs 1v 1.4v digital soft-start reference 1.23v n 210 s delay bootstrap uvlo 21.6v 9.74v functional diagram package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 10 max u10+2 21-0061 90-0330
max17499/max17500 current-mode pwm controllers with programmable switching frequency maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/10 initial release 1 7/11 changed operating temperature from -40c to +85c to -40c to +125c 1C4

▲Up To Search▲

Price & Availability of MAX17499BAUB

	To Download MAX17499BAUB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .